1. Field of the Invention
The present invention relates to a shift register and to a liquid crystal driving circuit including the same. More specifically, the present invention relates to a shift register used in a liquid crystal display for supplying scanning drive signals, and to a liquid crystal driving circuit including the shift register.
2. Description of the Related Art
Active-matrix liquid crystal displays (LCDs) used in, for example, computers and televisions include an array of video signal lines (source lines) and scanning drive signal lines (gate lines), and switching devices, such as thin-film transistors (TFTs), disposed at intersections of the video signal lines and the scanning drive signal lines for driving liquid crystal of pixels.
Scanning drive signals are supplied to the scanning drive signal lines to sequentially scan the signal lines so that all switching devices on a given scanning drive signal line are temporarily rendered into a conducting state (or an on state). In synchronization with the scanning drive signal lines, video signals are supplied to the video signal lines.
A shift register sequentially supplies the scanning drive signals to the scanning drive signal lines.
FIG. 8 is a circuit diagram of a shift register of the related art. Although the shift register includes multiple stages, three of them, e.g., stages i−1, i, and i+1, are shown in FIG. 8. FIG. 9 is a timing chart of the shift register shown in FIG. 8.
As shown in FIG. 8, each of the stages i−1, i, and i+1 is composed of four transistors and one capacitor. This structure does not place excessive stress on the transistors, and reduces deterioration of transistor characteristics.
For example, focusing on the stage i, a diode-connected input transistor 51 is connected to an output node Gi−1 of the preceding stage i−1, and an output electrode of the input transistor 51 is connected to a control electrode of an output transistor 52 and a clamping transistor 53. An output electrode of the output transistor 52 is connected to a pull-down transistor 54. A capacitor 55 is connected between the control electrode and output electrode of the output transistor 52.
In this shift register, as shown in FIG. 8, a plurality of phase-shifted clock signals CKA, CKB, and CKC are input to the output transistors 52 of the stages i−1, i, i+1, and a control electrode of the clamping transistor 53 in a given stage is supplied with an output signal from the stage two stages after this stage.
In the stage i shown in FIG. 8, as shown in FIG. 9, when an output signal Gi−1 of the preceding stage i−1 is at a high level, the input transistor 51 is turned on, and an electric potential Vbi (control signal) of the control electrode of the output transistor 52 goes high. In this state, the output transistor 52 is turned on.
When the clock signal CKB input to the output transistor 52 is switched high, an output signal Gi of the stage i is switched high, and is then output.
When an output signal Gi+2 of the stage two stages after the stage i is switched high and is input to the control electrode of the clamping transistor 53 in the stage i, the clamping transistor 53 is turned on, and the electric potential Vbi of the control electrode of the output transistor 52 goes low. In this way, the output signals Gi−1, Gi, Gi+1 are sequentially output from the stages i−1, i, and i+1, respectively. This structure is useful for, for example, a scanning circuit in a liquid crystal display (see Japanese Unexamined Patent Application Publication No. 08-87897).
However, in the shift register disclosed in this publication, as shown in FIG. 9, the node indicated by the electric potential Vbi shown in FIG. 8 holds a voltage as high as or higher than the high-level voltage for a period of time three times longer than the pulse width of the clock signal, and supplies the high voltage to the control electrode (gate electrode) of the transistor 52.
In the shift register shown in FIG. 8, for example, an output pulse Gi+2 of the (i+2)-th stage is applied to the control electrode of the clamping transistor 53 in the stage i.
In this circuit operation, a voltage is still applied to the control electrode of the output transistor 52 after the output signal Gi is output from the stage i, and the output transistor 52 is maintained in the on state. When the clock signal CKB is switched low, the charge on the output line is discharged through the output transistor 52.
The pull-down transistor 54 is a non-switching transistor that is continuously conducting, and functions as a pull-down resistor whose output is maintained at the low level. The transistor 54 is not used to discharge a high-level output signal.
This circuit design overcomes a problem with traditional shift registers in that operation failure is caused by excessive stress placed on the pull-down transistor 54 when an inverting amplifier in an intermediate section of the shift registers is formed of the output transistor 52 and the pull-down transistor 54 of which the control electrode is connected to a constant voltage.
There are two solutions to this problem.
A first solution is that, as disclosed in the publication noted above, a voltage as high as a threshold voltage of the pull-down transistor 54, instead of a high-level signal (power supply voltage), is applied to the control electrode of the pull-down transistor 54 to reduce the stress on the pull-down transistor 54.
That is, a voltage that is slightly higher than the threshold voltage is applied to the control electrode of the pull-down transistor 54.
As described above, it is not desirable to increase the control voltage of the pull-down transistor 54. In order to ensure that the charge in the output terminal is discharged through the output transistor 52, an output signal of the (n+2)-th stage is applied to the control electrode of the clamping transistor 53 in the stage i to turn on the clamping transistor 53 while turning off the output transistor 52.
Alternatively, the clamping transistor 53 in the stage i may be turned on using an output signal of the stage i+1. Also in this case, as in the publication noted above, when the clock signal changes from high to low, the charge in the output terminal is discharged to the clock terminal through the output transistor 52. Thus, a demand exists for a circuit design for keeping the output transistor 52 in the on state for a while after the clock signal changes from high to low.
However, the voltage of the control electrode of the output transistor 52 and the voltage of the output terminal do not adjust each other. Due to the circuit design with limited flexibility, for example, characteristic deterioration of the output transistor 52 can cause unstable circuit operation.
A second solution is that a pulsed voltage signal is applied to the control electrode of the pull-down transistor 54 so as to activate the pull-down transistor 54 only when the output signal is reset (i.e., the output signal changes from high to low). The pull-down transistor 54 can be used to discharge the output signal.
That is, the charge is discharged not when the output terminal is reset, i.e., when the clock terminal is switched low, but when a resetting transistor is turned on.
Therefore, an additional circuit for applying a voltage to the control electrode of the pull-down transistor 54 for a short time is provided. This can cause problems of a complex circuit structure for applying a clock signal to a control electrode of an intermediate transistor and excessive stress placed on other transistors.
In particular, it is undesirable to apply repetitive voltages, e.g., clock signals, to the control electrode, as below.
As is well known in the art, D.C. voltages or clock signals continuously applied to a control electrode of a transistor cause changes of a threshold voltage, which is a voltage boundary between which the transistor is turned on and off, and a circuit including this transistor does not correctly operate.
The publication noted above takes measures against excessive stress on the pull-down transistor 54. However, an unnecessary voltage is still applied to the control electrode of the output transistor 52, thus preventing the shift register from shifting an output signal when the transistor 52 shown in FIG. 8 is not turned on by a predetermined threshold voltage due to threshold voltage variations.
For example, a shift register used in a scanning circuit of a liquid crystal display cannot shift output signals for sequentially driving scanning drive signal lines, resulting in no display on the screen.